Fault Tolerance and Performance of Multipath Multistage Interconnection Networks

In building a multiprocessor system, we can minimize the system's mean time to failure by providing an architecture resilient to component faults. We compare the fault tolerance and performance characteristics of various fault-tolerant multistage interconnection networks. We primarily focus on networks composed of dilated routing components. A dilated router features redundant outputs in each logical direction, and can thus be used to construct multipath networks. Multipath networks have multiple paths from any input to any output. An interwired multipath network disperses its routers' redundant outputs to input ports of physically distinct components. We introduce a deterministic wiring scheme for routing interwired networks that maximizes the number of routing paths available for each endpoint. We compare the deterministically-wired network to both randomlyinterwired networks and non-interwired multipath networks. We characterize fault tolerance by measuring the probability of a single endpoint disconnection as faults accumulate in the network. Our performance simulations are based on tra c from shared memory applications and include barrier synchronization to expose the effects of localized performance degradation. We nd that at a minor performance cost, deterministically-interwired networks are more fault tolerant than randomlyinterwired networks and non-interwired networks.